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3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM (Low power version with Self Refresh) HYB 314175BJ-50/-55/-60 HYB 314175BJL-50/-55/-60 Preliminary Information * * * * 262 144 words by 16-bit organization 0 to 70 C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 55 ns (-55 version) 60 ns (-60 version) CAS access time: 13ns (-50 & -55 version) 15 ns (-60 version) Cycle time: 89 ns (-50 version) 94 ns (-55 version) 104 ns (-60 version) Hype page mode (EDO) cycle time 20 ns (-50 & -55 version) 25 ns (-60 version) High data rate 50 MHz (-50 & -55 version) 40 MHz (-60 version) Single + 3.3 V (0.3 V) supply with a builtin VBB generator * * * * * * * * * * * * * * * Low Power dissipation max. 450 mW active (-50 version) max. 432 mW active (-55 version) max. 378 mW active (-60 version) Standby power dissipation 7.2 mW standby (TTL) 3.6 mW max. standby (CMOS) 0.72 mW max. standby (CMOS) for Low Power Version Output unlatched at cycle end allows twodimensional chip selection Read, write, read-modify write, CASbefore-RAS refresh, RAS-only refresh, hidden-refresh and hyper page (EDO) mode capability 2 CAS / 1 WE control Self Refresh (L-Version) All inputs and outputs TTL-compatible 512 refresh cycles / 16 ms 512 refresh cycles / 128 ms Low Power Version only Plastic Packages: P-SOJ-40-1 400mil width The HYB 314175BJ/BJL is the new generation dynamic RAM organized as 262 144 words by 16-bit. The HYB 314175BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 314175BJ/BJL to be packed in a standard plastic 400mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include Self Refresh (L-Version), single + 3.3 V ( 0.3 V) power supply, direct interfacing with high performance logic device families. Semiconductor Group 1 7.96 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Ordering Information Type HYB 314175BJ-50 HYB 314175BJ-55 HYB 314175BJ-60 HYB 314175BJL-50 HYB 314175BJL-55 HYB 314175BJL-60 Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L WE H H H H H L L L H OE H H L L L H H H H I/O1-I/O8 High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z I/O9-I/O16 High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write Ordering Code Q67100 - Q2148 on request Q67100 - Q2149 on request on request on request Package P-SOJ-40-1 P-SOJ-40-1 P-SOJ-40-1 P-SOJ-40-1 P-SOJ-40-1 P-SOJ-40-1 Description 3.3 V 50 ns 256 Kx16 EDO-DRAM 3.3 V 55 ns 256 Kx16 EDO-DRAM 3.3 V 60 ns 256 Kx16 EDO-DRAM 3.3 V 50 ns 256 Kx16 EDO- DRAM 3.3 V 55 ns 256 Kx16 EDO- DRAM 3.3 V 60 ns 256 Kx16 EDO-DRAM Pin Names A0-A8 RAS UCAS, LCAS WE OE I/O1 - I/O16 Address Inputs Row Address Strobe Column Address Strobe Read/Write Input Output Enable Data Input/Output Power Supply (+ 3.3 V) Ground (0 V) No Connection VCC VSS N.C. Semiconductor Group 2 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Pin Configuration (top view) P-SOJ-40-1 Semiconductor Group 3 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Block Diagram Semiconductor Group 4 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Absolute Maximum Ratings Operating temperature range ........................................................................................ 0 to + 70 C Storage temperature range..................................................................................... - 55 to + 150 C Input/output voltage ..................................................................................... - 1 to (VCC + 0.5, 4.6) V Power supply voltage................................................................................................... - 1 to + 4.6 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Input high voltage Input low voltage LVTTL Output high voltage (IOUT = - 2.0 mA) LVTTL Output low voltage (IOUT = 2 mA) LVCMOS Output high voltage (IOUT = - 100 A) LVCMOS Output low voltage (IOUT = 100 A) Input leakage current, any input (0 V < VIN < 7 V, all other inputs = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < VCC) Average VCC supply current: -50 version -55 version -60 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VIH) Average VCC supply current during RAS-only refresh cycles: -50 version -55 version -60 version Symbol Limit Values min. max. 2.4 - 1.0 2.4 - 2.4 - - 10 - 10 - 125 120 105 mA 2, 3, 4 Unit Notes V V V V V V A A 1 1 1 1 1 1 1 1 VIH VIL VOH VOL VOH VOL II(L) IO(L) ICC1 VCC + 0.5 0.8 - 0.4 - 0.4 10 10 ICC2 ICC3 - - 2 mA - 125 120 105 mA 2, 4 Semiconductor Group 5 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM DC Characteristics (cont'd) Parameter Average VCC supply current during hyper page mode (EDO) operation: -50 version -55 version -60 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode: -50 version -55 version -60 version Standby VCC current (L-version) (RAS = LCAS = UCAS = WE = VCC - 0.2 V) Self Refresh Current (L-version) (RAS, LCAS, UCAS = 0.2V A0 - A8 = VCC - 0.2 V or 0.2 V) Symbol - Limit Values min. max. Unit Test Condition 2, 3, 4 ICC4 115 115 100 mA ICC5 - - 1 mA 1 2, 4 ICC6 125 120 105 - - 200 250 mA ICC5 ICCS A A Capacitance TA = 0 to 70 C; VCC = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (A0 to A8) Input capacitance (RAS, UCAS, LCAS, WE, OE) Output capacitance (l/O1 to l/O16) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit CI1 CI2 CIO Semiconductor Group 6 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM AC Characteristics 5) 6) TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Symbol -50 Limit Values -55 -60 min max min max min max Unit Note Common Parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delaytime RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time(rise and fall) Refresh period Refresh period (L-version) tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF 89 35 50 8 0 8 0 8 12 10 13 40 5 1 - - - - 10k 10k - - - - 37 25 - - - 50 16 128 94 35 55 8 0 8 0 8 12 10 13 45 5 1 - - - - 10k 10k - - - - 43 30 - - - 50 16 128 104 40 60 10 0 10 0 10 14 12 15 50 5 1 - - - - 10k 10k - - - - 45 30 - - - 50 16 128 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7 Read Cycle Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time ref. to RAS CAS to output inlow-Z tRAC tCAC tAA tOEA tRAL tRCS tRCH tRRH tCLZ - - - - 25 0 0 0 0 50 13 25 13 - - - - - - - - - 25 0 0 0 0 55 13 25 13 - - - - - - - - - 30 0 0 0 0 60 15 30 15 - - - - - ns ns ns ns ns ns ns ns ns 8, 9 8, 9 8,10 11 11 8 Semiconductor Group 7 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Parameter Symbol -50 Limit Values -55 0 0 0 10 10 13 13 - - - 0 0 0 13 13 -60 15 15 - - - min max min max min max Unit Note Output buffer turn-off delay from CAS Data to OE low delay CAS high to data delay OE high to data delay tOFF 0 0 0 10 10 13 13 - - - ns ns ns ns ns 12 12 13 14 14 Output buffer turn-off delay from OE tOEZ tDZO tCDD tODD Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Data to CAS low delay tWCH tWP tWCS tRWL tCWL tDS tDH tDZC 8 8 0 13 13 0 8 0 - - - - - - - - 8 8 0 13 13 0 8 0 - - - - - - - - 10 10 0 15 15 0 10 0 - - - - - - - - ns ns ns ns ns ns ns ns 16 16 13 15 Read-modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 118 64 27 39 10 - - - - - 122 69 27 39 10 - - - - - 138 77 32 47 13 - - - - - ns ns ns ns ns 15 15 15 Hyper Page Mode (EDO) Cycle Hyper page mode cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in hyper page mode tHPC tCP tCPA tCOH tRAS 20 8 - 5 50 27 - - 27 - 20 8 - 5 - - 27 - 25 10 - 5 - - 32 - ns ns ns ns 7 200k 55 200k 60 200k ns RAS hold time from CAS precharge tRHCP - 27 - 32 - ns Semiconductor Group 8 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Parameter Symbol -50 Limit Values -55 -60 min max min max min max Unit Note Hyper Page Mode (EDO) Read-Modify-Write Cycle Hyper page mode read/write cycle time CAS precharge to WE delay time tPRWC tCPWD 58 41 - - 58 41 - - 68 49 - - ns ns CAS before RAS Refresh Cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write to RAS hold time tCSR tCHR tRPC tWRP tWRH 5 10 5 10 10 - - - - - 5 10 5 10 10 - - - - - 5 10 5 10 10 - - - - - ns ns ns ns ns CAS-before-RAS Counter Test Cycle CAS precharge time tCPT 35 - 35 - 40 - ns Self Refresh Cycle (L-Version only) RAS pulse width RAS precharge time CAS hold time tRASS tRPS tCHS 100 95 - - 100 110 - - 100 110 - - s ns ns - 50 - - 50 - - 50 - Semiconductor Group 9 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA, tCPA , tOEA. tCAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. Semiconductor Group 10 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Read Cycle Semiconductor Group 11 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Write Cycle (Early Write) Semiconductor Group 12 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Write Cycle (OE Controlled Write) Semiconductor Group 13 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Read-Write (Read-Modify-Write) Cycle Semiconductor Group 14 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Hyper Page Mode (EDO) Read Cycle Semiconductor Group 15 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Hyper Page Mode (EDO) Early Write Cycle Semiconductor Group 16 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycles Semiconductor Group 17 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM RAS-Only Refresh Cycle Semiconductor Group 18 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM CAS-Before-RAS Refresh Cycle Semiconductor Group 19 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM CAS before RAS Self Refresh Cycle (L-version only) Semiconductor Group 20 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Hidden Refresh Cycle (Read) Semiconductor Group 21 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Hidden Refresh Cycle (Early Write) Semiconductor Group 22 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM CAS/-Before-RAS Refresh Counter Test Cycle Semiconductor Group 23 HYB 314175BJ/BJL-50/-55/-60 3.3V 256K x 16 EDO-DRAM Package Outline Plastic Package, P-SOJ- 40-1 (SMD) (Plastic Small Outline J-leaded Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 24 Dimensions in mm GPJ09018 |
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